SAA7111, Elektronika, elementy
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INTEGRATED CIRCUITS DATA SHEET SAA7111 Video Input Processor (VIP) Product specification Supersedes data of 1996 Oct 30 File under Integrated Circuits, IC22 1998 May 15 Philips Semiconductors Product specification Video Input Processor (VIP) SAA7111 CONTENTS 16.2.10 Subaddress 0A 16.2.11 Subaddress 0B 16.2.12 Subaddress 0C 16.2.13 Subaddress 0D 16.2.14 Subaddress 0E 16.2.15 Subaddress 10 16.2.16 Subaddress 11 16.2.17 Subaddress 12 16.2.18 Subaddress 1A (read-only register) 16.2.19 Subaddress 1B (read-only register) 16.2.20 Subaddress 1C (read-only register) 16.2.21 Subaddress 1F (read-only register) 17 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 Analog input processing FILTER CURVES 8.2 Analog control circuits 17.1 Anti-alias filter curve 8.2.1 Clamping 17.2 Luminance filter curves 8.2.2 Gain control 17.3 Chrominance filter curves 8.3 Chrominance processing 18 I 2 C START SET-UP 8.4 Luminance processing 8.5 RGB matrix 19 PACKAGE OUTLINE 8.6 VPO-bus (digital outputs) 20 SOLDERING 8.7 Synchronization 20.1 Introduction 8.8 Clock generation circuit 20.2 Reflow soldering 8.9 Power-on reset and CE input 20.3 Wave soldering 8.10 RTCO output 20.3.1 PLCC 8.11 The Line-21 text slicer 20.3.2 QFP 8.11.1 Suggestions for I 2 C-bus interface of the display software reading line-21 data 20.3.3 Method (PLCC and QFP) 20.4 Repairing soldered joints 9 GAIN CHARTS 21 DEFINITIONS 10 LIMITING VALUES 22 LIFE SUPPORT APPLICATIONS 11 CHARACTERISTICS 23 PURCHASE OF PHILIPS I 2 C COMPONENTS 12 TIMING DIAGRAMS 13 CLOCK SYSTEM 13.1 Clock generation circuit 13.2 Power-on control 14 OUTPUT FORMATS 15 APPLICATION INFORMATION 15.1 Layout hints 16 I 2 C-BUS DESCRIPTION 16.1 I 2 C-bus format 16.2 I 2 C-bus detail 16.2.1 Subaddress 00 16.2.2 Subaddress 02 16.2.3 Subaddress 03 16.2.4 Subaddress 04 16.2.5 Subaddress 05 16.2.6 Subaddress 06 16.2.7 Subaddress 07 16.2.8 Subaddress 08 16.2.9 Subaddress 09 1998 May 15 2 Philips Semiconductors Product specification Video Input Processor (VIP) SAA7111 1 FEATURES · Four analog inputs, internal analog source selectors, e.g. 4 ´ CVBS or 2 ´ Y/C or (1 ´ Y/C and 2 ´ CVBS) · Two analog preprocessing channels · Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel · Two switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0) via the I 2 C-bus · Switchable white peak control · Two built-in analog anti-aliasing filters · Chip enable function (reset for the clock generator) · Two 8-bit video CMOS analog-to-digital converters (ADCs) · Compatible with memory-based features (line-locked clock) · On-chip clock generator · Boundary scan test circuit complies with the IEEEStd. 1149.1 - 1990 (ID-Code = 0 7111 02 B) · Line-locked system clock frequencies · Digital PLL for H-sync processing and clock generation · I 2 C-bus controlled (full read-back ability by an external controller). · Requires only one crystal (24.576 MHz) for all standards · Horizontal and vertical sync detection 2 APPLICATIONS · Automatic detection of 50/60 Hz field frequency and automatic switching between standards PAL and NTSC · Desktop video · Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and NTSC 4.43 · Multimedia · Digital television · Image processing · User programmable luminance peaking or aperture correction · Video phone. · Cross-colour reduction for NTSC by chrominance comb filtering 3 GENERAL DESCRIPTION · PAL delay line for correcting PAL phase errors The Video Input Processor (VIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M and NTSC N), a brightness/contrast/saturation control circuit and a colour space matrix (see Fig.1). · Real time status information output (RTCO) · Brightness Contrast Saturation (BCS) control on-chip · The YUV (CCIR-601) bus supports a data rate of: – 864 f H = 13.5 MHz for 625 line sources – 858 ´ f H = 13.5 MHz for 525 line sources. The CMOS circuit SAA7111, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL and NTSC signals into CCIR-601 compatible colour component values. The SAA7111 accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I 2 C-bus controlled. · Data output streams for 16, 12 or 8-bit width with the following formats: – 411 YUV (12-bit) – 422 YUV (16-bit) – 422 YUV [CCIR-656] (8-bit) – 565 RGB (16-bit) with dither – 888 RGB (24-bit) with special application. · 720 active samples per line on the YUV bus · One user programmable general purpose switch on an output pin · Built in line-21 text slicer · Power-on control 1998 May 15 3 ´ Philips Semiconductors Product specification Video Input Processor (VIP) SAA7111 4 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT V DDD digital supply voltage 4.5 5.0 5.5 V V DDA analog supply voltage 4.75 5.0 5.25 V T amb operating ambient temperature 0 25 70 ° C P A+D analog and digital power 0.77 1.0 1.26 W 5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA7111WP PLCC68 plastic leaded chip carrier; 68 leads SOT188-2 SAA7111H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 SOT393-1 ´ 14 ´ 2.7 mm 1998 May 15 4 Philips Semiconductors Product specification Video Input Processor (VIP) SAA7111 6 BLOCK DIAGRAM handbook, full pagewidth BYPASS AOUT 23 (14) AI11 AI12 21 (12) 19 (10) ANALOG PROCESSING AND ANALOG-TO- DIGITAL CONVERSION CHROMINANCE CIRCUIT YUV-to-RGB CONVERSION AND 45 to 50 53 to 62 (34 to 39) (42 to 51) VPO (0 : 15) AND BRIGHTNESS CONTRAST SATURATION C/CVBS OUTPUT 17 (8) 15 (6) UV FORMATTER (52) 63 AI21 AI22 FEI CONTROL Y (31) 42 AD2 AD1 HREF n.c. 7,8,9 (64) 22 (13) V SS CON Y I C-BUS CONTROL (53) 64 GPSW ANALOG 10,36, 37 LUMINANCE CIRCUIT I C-BUS PROCESSING (61) 4 n.c. INTERFACE IICSA CONTROL Y/CVBS (62) 5 SDA (63) 6 SCL Y V SSA1-2 V DDA1-2 18,14 (9,5) 20,16 (11 ,7) SAA7111 CLOCKS TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST (54) 65 XTAL XTALI TDI 12 (3) CLOCK (55) 66 TCK 2 (59) 13 (4) 1 (58) GENERATION CIRCUIT SYNCHRONIZATION CIRCUIT (21) 30 (22) 31 (20) 29 TMS LLC2 CREF TRST POWER-ON CONTROL LLC LFCO 11 (2) (23) 32 TDO RES (57,41,33,25,18) 68,52,44,34,27 (56,40,32,26,19) 67,51,43,35,28 (30) 41 (27) 38 (17) 26 (29) 40 (28) 39 (60) 3 (15) 24 (16) 25 (24) 33 MGC653 V DD1-5 V SS1-5 VS HS VREF RTS0 RTS1 RTCO V DDA0 V SSA0 CE The pin numbers given in parenthesis refer to the 64-pin package. Fig.1 Block diagram. 1998 May 15 5 2 2 [ Pobierz całość w formacie PDF ] |